Design and evaluation of variable stages pipeline processor with low-energy techniques
Tomoyuki Nakabayashi, Tomonari Sasaki, Kazuhiko Ohno, T. Kondo · IET Computers & Digital Techniques · 2012
Enhancement of mobile computers requires high-performance computing with low-energy consumption. Variable stages pipeline (VSP) architecture, which reduces energy consumption and improves execution time by dynamically unifying the pipeline stages, is proposed to achieve this requirement. A VSP processor uses a special pipeline register called a latch D-flip-flop selector-cell (LDS-cell) that unifies the pipeline stages and prevents glitch propagation caused by stage unification under low-energy mode. The design of the fabricated VLSI of a VSP processor chip on 0.18 µm CMOS technology is presented. An evaluation shows that the VSP processor consumes 13% less energy than a conventional one.