Dynamic Zero-Sensitivity Scheme for Low-Power Cache Memories
Yen‐Jen Chang, Feipei Lai · IEEE Micro · 2005
A low-power cache has become essential in many applications, but cache accesses contribute significantly to a chip's total power consumption. Because most bit values read from the cache are 0's, the authors introduce a dynamic zero-sensitivity (DZS) scheme that reduces average cache power consumption by preventing bitlines from discharging in reading a 0.