Configuring algorithm for reconfigurable Network-on-Chip architecture
Hui Ding, Huaxi Gu, Bin Li, Keming Du · 2012
With the challenge that a larger number of cores will be integrated on one single chip, Network-on-Chip (NoC) has been the popular solution gradually. And recently, researchers have focused on improving the performance of NoC to achieve well-performed chips. In this paper, we will propose a configuring algorithm based on one reconfigurable NoC architecture to design application-specific NoC. The reconfigurable NoC architecture decreases the design complexity and makes NoC design more flexible comparing to the topology-generation-floorplanning scheme and mapping scheme respectively. Besides, our configuring algorithm aims at optimized networks with better performance. For one specific application, we can choose the reconfigurable NoC architecture with suitable size and configure it according to the communication relationship to make sure that the final network is optimized. A cycle-accurate simulator is used to carry out simulations for three networks designed by our scheme and two other methods for the same application under the same environment. The results turn out that our network performs better.