A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache
Stefan Rusu, Simon M. Tam, Harry Muljono, David Ayers, J. Chang, B.S. Cherkauer, Jason Stinson, John Benoit, Raj Varada, Justin Leung, Rahul Limaye, Shashwat Vora · IEEE Journal of Solid-State Circuits · 2007
This paper describes a dual-core 64-b Xeon MP processor implemented in a 65-nm eight-metal process. The 435-mm2die has 1.328-B transistors. Each core has two threads and a unified 1-MB L2 cache. The 16-MB shared, 16-way set-associative L3 cache implements both sleep and shut-off leakage reduction modes. Long channel transistors are used to reduce subthreshold leakage in cores and uncore (all portions of the die that are outside the cores) control logic. Multiple voltage and clock domains are employed to reduce power