Functional verification methodology for the PowerPC 604 microprocessor
James Monaco, David Holloway, Rajesh Raina · 1996
Functional (i.e., logic) verification of the current generation of complex, super-scalar microprocessors such as the PowerPC 604 microprocessor presents significant challenges to a project's verification participants. Simple architectural level tests are insufficient to gain confidence in the quality of the design. Detailed planning must be combined with a broad collection of methods and tools to ensure that design defects are detected as early as possible in a project's life-cycle. This paper discusses the methodology applied to the functional verification of the PowerPC 604 microprocessor.