FPGA-based implementation of single-precision exponential unit
Christopher Doss, R. L. Riley · 2004
This work explores the feasibility of implementing a floating-point exponentiation unit on reconfigurable computing systems. A table-driven exponentiation unit was implemented using synthesizable VHDL. The hardware implementation was performed using the same methodology as Bui et. al. We first implemented the individual components required to perform the exponentiation operation. These include such operations as IEEE-754 floating-point addition, multiplication, comparison, and power of two. These modules were then linked together to form the overall unit. The designs were synthesized, placed and routed. Results indicate that today's FPGAs are well suited for this operation. The exponentiation unit was simulated, synthesized, and placed and routed to a Xilinx Virtex 2 4000 part with a speed grade of 5. The unit requires 5564 of the available 23,040 slices, and is capable of operating at 87 MHz.