A TDMA/TDD processing unit IP core for WLL cell station targeting FPGA implementation
Israsena, Wattanawong, Meenakarn, Chupayak, Yutana Jewajinda, Duangtanoo, Juakvont · 2003
This paper describes how the TDMA/TDD processing unit, which is conventionally implemented as an ASIC, can be successfully adopted using FPGA technology. The TDMA/TDD soft IP, with its internal memory requirement, is particularly suitable for FPGA implementation. The design was successfully tested at the laboratory stage as a component for a cell station of a PHS wireless system to be used in wireless local loop system as a viable alternative for rural telephone systems. The core, when implemented on a cost-effective FPGA, is able to operate at up to 30MHz.