Design of any codeword length parallel long BCH encoders with the help of an efficient C-utility
Sagar Koorapati, Surya Prakash M · 2015
Error correction has become crucial for NAND Flash based Solid State Drives. As we move towards MLC (Multi Level Cell) NAND Flash memories from SLC (Single Level Cell) NAND Flash memories to achieve higher data density at lower cost per storage unit, we see increased Bit Error Rate (BER) in MLC NAND memories. BCH (Bose-Chaudhuri- Hocquenghem) codes are popular to detect and correct such higher number of errors in many communication applications in addition to the storage domain. BCH encoders are conventionally implemented by linear feedback shift registers that can be directly derived from Generator Polynomial. This direct implementation of long BCH encoders is not suitable for high speed applications, demanding high speed parallel long BCH encoder architectures. One potential problem with such high speed parallel long BCH encoders is its routing complexity when realizing the encoders in hardware. In this paper, we present the design of a long parallel BCH encoder ((4928, 4096) BCH code) with the help of a simple and efficient C-utility. This C-utility takes Generator Polynomial, unfolding factor parameter as inputs, generates the Data Flow Graph in terms of nodes, connectivity matrix with delay elements; generates the resulting BCH encoder hardware code (Verilog RTL code). The proposed C-utility can be used to auto generate any codeword length BCH encoder hardware for configurable unfolding factor value, thus avoiding the RTL design and implementation of encoder, simplifying and speeding up the encoder design compared to the conventional encoder design approaches. The proposed C-utility also generates enough details for each design configuration to analyze the routing complexity of the design much in advance.