High-efficiency test pattern generating mechanism
Chuen-Yau Chen · International Journal of Electronics · 2008
A high-efficiency test pattern generating mechanism blending the weighted-random-pattern generator and the controllable-linear-feedback-shift register is proposed in this paper. This mechanism tests a logic circuit in two phases. In the first phase, the weighted-random-pattern generator generates the test patterns to drop some of the faults from the fault list containing the faults that have not been tested in the initial testing performed by the patterns generated from the automatic-test-pattern generator. In the second phase, the controllable-linear-feedback-shift register generates the test patterns to test the deterministic faults that have not been tested in the first phase. We adopt controllable-linear- feedback-shift register to generate the deterministic patterns instead of modifying the configuration of the weighted-random-pattern generator such that a better fault coverage can be achieved with a lower hardware penalty and a shorter test length.