A fast and low cost self-routing permutation network
J.P. Agrawal, Yixin Zhang · IEEE Transactions on Computers · 1998
In this paper, we present a new implementation of the fast VLSI-efficient self-routing N/spl times/N permutation network proposed by Cam and Fortes, which requires only about half as much hardware and has a lower latency. Cam and Fortes' implementation uses Cormen and Leiserson's hyperconcentrators, which can route only active inputs. The reduction in hardware is achieved by modifying Cormen and Leiserson's hyperconcentrator to route active, as well as inactive, inputs to the output. This modification allows us to reduce the number of hyperconcentrators needed in the permutation network by 50 percent and eliminate the interstage interconnection networks, making the permutation network faster by log/sub 2/N bits.