A novel processor design flow using processor description language applied to a vector coprocessor
Makiko Ito, Mitsuru Tomono, Yi Ge, Y. Takebe, M. Toichi, Makoto Mouri, Yoshihiro Hirose · 2013
We have developed a vector coprocessor for a wireless baseband SoC for mobile devices using processor description language. The design of the vector coprocessor is highly-complex and it requires a lot of design time and costs with a conventional design flow. To address this problem, we developed an architecture design flow with an untimed model and a performance estimator. We achieved 4.5 times better design efficiency compared to a conventional implementation design flow with a timed model. As a result, we were able to reduce design and optimization time dramatically.