Failure-Erasure Circuitry: A Duplicative Technique of Failure-Masking Systems
J. B. Connolly, William G. Schmidt · IEEE Transactions on Electronic Computers · 1967
This paper describes a logical redundancy technique based on failure-erasure circuitry that is capable of automatically masking as many as P-1 individual failures in P identical elements connected in parallel. This technique is contrasted with the standard von Neumann scheme where only (P/2) such failures can be tolerated. In order to prevent the effect of any single failure from propagating, each logical element in the original network need only be duplicated rather than triplicated as in the von Neumann technique. The usefulness of the redundancy technique described is predicated on the existence of circuitry that fails to a NULL state rather than to a ZERO or ONE state. Accordingly, several circuits which exhibit the desired failure mode and that are worthy of further development for reliability applications are discussed.