Reconfigurable digital sequential system on chip design with its analysis of various parameters & power reduction using dynamic partial reconfiguration
Navneet Kumar Agrawal, Mayuri Jain · 2013
In this paper, we have designed a Reconfigurable Digital Sequential System on Chip design capable of transmitting and receiving data in parallel in 8 bits to 512 bits range. This circuit provides Reconfigurable point to point communication, data rate of 1.54 Gbits/sec to 277 Gbits/sec. The design comprises of two Sub Circuits: Transmitter/Receiver & Router. Our objective after developing Reconfigurable system was reduction of the power consumption in the circuit by exploiting Dynamic Partial Reconfiguration, which we get after results is nearly 5% - 10% of the total power consumption of the circuit and finally we have concluded the calculated parameters i.e. Power Consumption (Static and Dynamic), Delay, data rate and Resources Utilized by taking all the Reconfigurable Transreciever as platform on the various FPGA families by Xilinx and finally plot them on graph, so as to exploit respective family according to application, specification as well as constraints what is the best chosen parameter and family according to the analysis made. The complete circuit is programmed in VHDL, and synthesized and simulated on Xilinx design suite 14.4 ISE.