A cost-efficient high-performance bit-serial architecture for robot inverse dynamics computation
Mahibur Rahman, David G. Meyer · IEEE Transactions on Systems Man and Cybernetics · 1987
A novel cost-efficient parallel and pipelined bit-serial array architecture is proposed for the computation of robot inverse dynamics. It achieves a certain bit-serial execution-time lower bound. The core of the system consists of two arrays of multifunctional bit-serial cells. One of the arrays computes the forward iterations, and the other one evaluates the backward recursions, of the Newton-Euler dynamics algorithm. At the current state of technology, the resulting high-performance system may be realized in only two custom VLSI chips and a minimum number of first-in-first-out register files. The organization, operation, and performance of the proposed array structure is discussed. The architecture and functionality of an individual multifunctional bit-serial cell used as the building block of the array structure is described.