VLSI architecture of wavelet transform based on basic lifting elements
Jie Guo, Yunsong Li, Keyan Wang, Chengke Wu · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2009
In this paper, we propose a lifting architecture based on a basic lifting unit, whose structure performs lifting operations in a repetitive way. By analyzing computational processes in lifting in detail, the reusable Basic Lifting Element (BLE) is presented. The BLE structure is designed and optimized from the viewpoint of hardware implementation. The proposed lifting processor can be executed by arranging BLEs repeatedly. Experimental results show that the proposed architecture can transform any size of tiles with 9/7 filter and 5/3 filter for lossy and lossless compression, respectively. The lifting processor is designed in Verilog HDL and synthesized into Xilinx FPGA, which can run up to 130MHz.