SH-5: the 64 bit superH architecture
Partha Pratim Biswas, Atsushi Hasegawa, S. Mandaville, Mark Debbage, Andy Sturges, F. Arakawa, Yuichi Saito, Kota Uchiyama · IEEE Micro · 2000
A collaborative effort of Hitachi and STMicroelectronics, the SH-5 is the latest member of the SuperH microprocessor series. Its CPU core is the first implementation of a new instruction set architecture consisting of 32-bit instructions, 64-bit registers, SIMD (single-instruction, multiple-data) instructions for multimedia applications, and a compatibility mode supporting the 16-bit SuperH instruction set. Embodying an emerging philosophy of embedded-core design, the SH-5 provides a platform for a wide range of applications: set top cable boxes, digital TV, voice over IP (Internet telephony), network processing, PDAs (personal digital assistants), Internet appliances, in-car information systems, game machines, and so on. A single cost-effective, optimum design that will cater to the requirements of such a wide range of applications is not feasible. So the SH-5 core supports a carefully selected set of functions critical to meeting the performance, power, and code-size requirements of these applications. At the same time, it: provides features that ease integration into a system on chip (SOC) that uses application-specific hardware modules to cater to specific requirements.