VLSI implementation of digital channeliser using distributed arithmetic
Richard Qi, F.P. Coakley · Electronics Letters · 1992
A VLSI architecture for a digital channeliser based on the time-multiplexed tree filter bank is described, in which the maximum sharing of the arithmetic operations at each stage is achieved. A very efficient implementation of the band-splitting filter is achieved by using distributed arithmetic, allowing a single chip design that does not require multipliers for an 8 channel channeliser.