A Design Flow to Map Parallel Applications onto FPGAs
Sébastien Le Beux, Philippe Marquet, Jean‐Luc Dekeyser · 2007
This paper introduces a new flow able to fit a parallel application onto an FPGA according to the FPGA characteristics such as computing power and IOs. The flow is based on iterative refactoring and transformations of the application. From the resulting application, a VHDL code is generated. This code is finally used to simulate or synthesize the application. Significant experiments have validated the approach.