Memory efficient VLSI architecture for lifting-based DWT
Anand D. Darji, Ankur Limaye · 2014
In this paper, a new lifting-based DWT architecture for CDF 9/7 filter is proposed which has lowest temporal memory among the existing architectures. This is achieved with a modified overlapped-scanning method and recalculation of one intermediate DWT coefficient. The proposed architecture requires only 2N temporal memory to process N × N sized image. The architecture has a critical path of one multiplier delay and demonstrates 100% hardware utilization efficiency.