Accurate and High-Speed Asynchronous Network-on-Chip Simulation Using Physical Wire-Delay Information
Takahiro Hanyu, Yuma Watanabe, Atsushi Matsumoto · 2013
A performance-evaluation simulator is a key tool for exploring appropriate asynchronous Network-on-Chip (NoC) architecture in early stage of LSI design. This paper presents a highly accurate performance-evaluation simulator with maintaining a short evaluation time for designing a high-performance asynchronous NoC. The use of a precise asynchronous-router circuit model, whose physical parameters such as wire delays as well as unit gate delays are preliminarily obtained using LSI CAD tool, makes it accurate to simulate asynchronous NoC systems. As a design example, multi-core asynchronous mesh-structured NoC systems are simulated by both the previous method and the proposed one whose results, such as latency and throughput, are validated with a highly precise transistor-level simulation result. As a result, the proposed simulator achieves almost the same accuracy as the corresponding gate-level simulators, while its simulation speed is one-thousand-times faster than that of the gate-level one at the packet injection rate of 30 (packets/?sec).