NETWORK PROCESSOR FOR HIGH-SPEED NETWORK AND QUICK PROGRAMMING
Takahiro Murooka, Akira Nagoya, Toshiaki Miyazaki, Hiroyuki Ochi, Yukihiro Nakamura · Journal of Circuits Systems and Computers · 2007
The paper describes the concept, architecture, and prototype test results of a packet processor that enables us to implement an application-specific high-speed packet processing system without expert-level programming skills. This processor has a pipelined processing architecture and features coarse-grained instructions that are based on the data formats of the telecommunication packet. Using this processor, target applications can be implemented within a short working period without degrading the processing performance. We implemented a prototype system to evaluate its packet propagation delay and packet forwarding performance. The measured results suggest that the architecture is useful for packet processing on high-speed telecommunication networks.