Dynamic hit logic with embedded 8Kb SRAM in 45nm SOI for the zEnterprise™ processor
A.R. Pelella, Y.H. Chan, Bargav Balakrishnan, Pradip Patel, D. Rodko, Richard Serton · 2011
With the push to ever higher core frequencies, more logic functions are making their way onto critical path SRAMs in the L1 cache look up structure. Described in this paper is a 14 bit dynamic hit logic scheme with an embedded 8K bit SRAM in IBM's 45nm SOI. The hit logic uses a "search-for-a-hit" scheme (i.e., XOR's followed by AND functions, pre-charged to a miss) to provide optimal performance, timing, and power. A custom microcode programmable Array-Built -In-Self-Test (ABIST) engine tests both the SRAM and hit logic function jointly, resulting in comprehensive "at-speed" test coverage to guarantee circuit functionality and timing margins. The SRAM is organized as a 64x15bx8W (way, or set) array and uses a 6T SRAM cell (1Read/1Write, 0.462μm2) in a "domino" hierarchal dual read bitline approach.