Efficient AFT implementation in FPGAs to detect potential electromigration failures
SAI DEEPA RAYAPROLU, Srikanth Vemuru, Mohammed Y. Niamat · 2012
An efficient and modular architecture is used to implement Arithmetic Fourier Transform algorithm as a Built-in-Self Test structure to identify electromigration faults in FPGAs. Xilinx Virtex 5 FPGA, implemented in 65 nm fabrication process, is used to implement BIST and simulate the electromigration failure mechanisms. Fault signatures are developed for different interconnect FPGA resources and simulation results are presented.