Cost-effectively offering private buffers in SoCs and CMPs
Zhen Fang, Li Zhao, Ravishankar Iyer, Carlos Flores Fajardo, German Fabila Garcia, Seung Eun Lee, Bin Li, Steve R. King, Xiaowei Jiang, Srihari Makineni · 2011
High performance SoCs and CMPs integrate multiple cores and hardware accelerators such as network interface devices and speech recognition engines. Cores make use of SRAM organized as a cache. Accelerators make use of SRAM as special-purpose storage such as FIFOs, scratchpad memory, or other forms of private buffers. Dedicated private buffers provide benefits such as deterministic access, but are highly area inefficient due to the lower average utilization of the total available storage.