Integrated processor architecture for multisensor signal processing
Robert E. Nasburg, Steve M. Stillman, M. T. Nguyen · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 1991
Sensor systems being conceived and fabricated today have high processor content and tend to be software intensive. Recent advances in hardware technology have made possible the implementation of complex high-performance multisensor algorithms. Hardware capability alone is not sufficient to ensure the successful implementation of these software intensive systems. In addition, it is necessary to carefully structure the processing system to ensure that high-performance multisensor algorithms can be implemented. Traditionally, implementability has meant throughput and memory capacity. This paper extends implementability to include the ability of a processing system architecture to support efficient integration and test. This is particularly important when the implicit requirements of cost and schedule are considered. To illustrate processor architecture impact on integration and test, an example from the LOWKATER program is examined. This was an extremely complex multisensor processor containing a digital laser radar receiver, a passive sensor target detector, and a digital controller for the beam pointing system. Architectural alternatives are presented and the selected architecture is examined in detail.