Othello Solver based on a soft-core MIMD processor array
Takayuki Mabuchi, Takahiro Watanabe, Retsu Moriwaki, Yuji Aoyama, Amarjargal Gundjalam, Yuichiro Yamaji, Hironari Nakada, Minoru Watanabe · 2010
This report presents an Othello Solver based on a 32-bit original soft-core Multiple Instruction stream, Multiple Data stream (MIMD) processor array targeting a single field programmable gate array (FPGA), Cyclone II (EP2C70D896C6N), on a DE2 Development and Education Board (Altera Corp.). The solver can execute a move-checking operation, a disc flipping operation, a move selection operation, an evaluation operation, and an alpha-beta pruning operation. The solver system includes a universal asynchonous receiver transmitter (UART) inside the FPGA and uses a RS-232C driver on the board so that the solver system can communicate with a personal computer or another FPGA according to the 2010 International Conference on Field Programmable Technology (FPT) competition specifications. The solver can win all skill levels of a target software provided from the FPT conference within the time limit of 1/40 s. This report presents estimates the solver's performance based on the implementation results.