Static Test Compaction for Scan Circuits by Using Restoration to Modify and Remove Tests
Irith Pomeranz · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2014
This paper describes a new approach to static test compaction for scan circuits that modifies tests in order to reduce the number of tests in a test set. The main contribution of this paper is a procedure referred to as restoration. In a basic step, the restoration procedure considers two tests, tremand tmod, with sets of detected faults Dremand Dmod, respectively. Starting from tnew= tmod, and considering tnewas a variation of trem, the procedure restores bits of treminto tnewas necessary to ensure that faults from Dremare detected by tnew. The procedure then restores bits of tmodinto tnewas necessary to ensure that all the faults from Dmodare detected by tnew. The test tnewis used for replacing tmod, and the faults it detects out of Dremare moved to Dmod. After several such steps, if Drem becomes empty, tremcan be removed from the test set. The procedure is applied to test sets that are already compacted. The results show that the procedure can achieve significant additional compaction even without considering all the tests for removal or modification.