A new multistandard video processor including deflection drive circuits which is controlled by digital process
Yoshihiro Baba, N. Yamazaki, Y. Sengoku, S. Nishiyama, H. Shimizu · IEEE Transactions on Consumer Electronics · 1989
The authors describe a novel multistandard video processor which uses the counted-down method in the synchronization block. The processor consists of luminance, chrominance and deflection signal processing blocks. The count-down method is used in both the horizontal and the vertical synchronization circuits of the deflection signal processing block. Because a 50/60 identification circuit is installed and the chrominance signal processing block can receive PAL (phase alteration line) and NTSC (National Television System Committee) signals using this video processor and a SECAM (sequential and memory) decoder, it is possible to construct a multistandard system TV receiver. Systematic development work has been done to maximize the performance of the functional blocks and to minimize the number of pins and external components.>