Dynamic reconfiguration of modular I/O IP cores for avionic applications
Venkatasubramanian Viswanathan, Benjamin Nakache, Rabie Ben Atitallah, Maurice Nakache, Jean‐Luc Dekeyser · 2012
Dynamic reconfiguration using FPGAs has been demonstrated to be highly efficient in different application domains. However little has been explored in the avionic communication domain, where halting the system during runtime for changing the hardware is non-trivial. In this paper we present a runtime reconfigurable architecture using I/O Intellectual Property (IP) cores, used in avionic applications. The system provides a modular I/O interface for communication, using an FPGA Mezzanine Card (FMC). User application can dynamically install and execute the necessary hardware for communication with external avionic sub-systems using FMC. The system thus provides a highly modular and cost effective autonomous solution for an embedded avionic communication system using Dynamic Partial Reconfiguration (DPR). The above described solution has been tested using a Xilinx ML605 prototyping board providing a software interface with a Xilinx Microblaze processor core. The architecture has been evaluated with the JPEG application in terms of area utilization, reconfiguration latency and execution time. The reconfiguration latency can be hidden totally in many cases. While in certain others, the overhead of reconfiguration can be justified by the reduction in the resource utilization.