A buffer merging technique for reducing memory requirements of synchronous dataflow specifications
Praveen K. Murthy, Shuvra S. Bhattacharyya · 1999
Synchronous Dataflow, a subset of dataflow, has proven to be a good match for specifying DSP programs. Because of the limited amount of memory in embedded DSPs, a key problem during software synthesis from SDF specifications is the minimization of the memory used by the target code. We develop a powerful formal technique called buffer merging that attempts to overlay buffers in the SDF graph systematically in order to drastically reduce data buffering requirements. We give a polynomial-time algorithm based on this formalism, and show that code synthesized using this technique results in more than a 60% reduction of the buffering memory consumption compared to existing techniques. 1 Introduction Memory is an important metric for generating efficient code for DSPs used in embedded applications. This is because most DSPs have very limited amounts of onchip memory, and adding off-chip memory is frequently not a viable option due to the speed, power, and cost penalty this entails. High-lev...