Systolic VLSI realization of a novel iterative division algorithm over GF(2/sup m/): a high-speed, low-complexity design
Chien-Hsing Wu, Chien‐Ming Wu, Ming‐Der Shieh, Yin‐Tsung Hwang · 2002
We present a parallel-in parallel-out systolic division circuit over GF(2/sup m/) based on the novel extended Stein's algorithm that provides guaranteed convergence in 2/sup m/-1 iterations. The area-time (AT) complexity of our design is O(m/sup 2/) and the achievable maximum clock rate is 1 GHz based on the 0.6 /spl mu/m technology. Compared to the best systolic design known to date based on the extended Euclid's algorithm the proposed circuit exhibits significant area and speed advantages.