Performance analysis of single stage interconnection networks
J.R. Burke, Changbin Chen, T.-Y. Lee, Dharma Prakash Agrawal · IEEE Transactions on Computers · 1991
A single-stage interconnection network (SSIN) consisting of only one stage of switches and recirculation through processors is studied. An analytical probability model for SSINs using 2*2 switches is introduced, and results obtained with the model are compared with simulation results. Four SSINs with different network sizes, loading, and routing strategies are discussed. Processors with and without buffers are considered, and three different routing strategies are applied to resolve conflicts. The analytical model is seen to be in close agreement with the simulation results while providing at least an order of magnitude reduction in CPU time.>