Modeling the effects of DFS on power consumption in hybrid chip multiprocessors
Ami Marowka · 2013
The power wall is one of the primary stumbling blocks that many-core microprocessor architecture is facing today. To avoid this problem, microprocessor makers are shifting towards heterogeneous chips that integrate different core architectures on a single die and that have proved to deliver better performance per watt. Moreover, these new hybrid microprocessors are equipped with dynamic frequency-scaling techniques that are capable of reducing total system power consumption.