Design and implemetion of DDR2 wrapper for cluster based MPSoC
Zhuo Liu, Gaoming Du, Duoli Zhang, Yukun Song, Li Li, Hong‐Bin Pan · 2010
Network on Chip (NoC) has emerged as a competitive and efficient communication infrastructure for multi-core System on Chip, of which there are three kind of components, processing element(processor, memory, IP, etc), communication element(such as router) and interface module between router and PE. One of the key problems is how to solve the memory bottleneck under the circumstances that multiple processing nodes access memories at the same time. In this paper, a cluster based MPSoC is designed, using Packet Connect Circuit (PCC) rout technique as the inter-cluster communication backbone. And the processing elements are grouped as a cluster, in which there usually consists of several processors and other IPs. Special effort is focused on the DDR2 interface design that can provide memory access through PCC between clusters and off-chip memory. The DDR2 wrapper links a DDR2 SDRAM to one of the router nodes. Dedicate circuit has been designed to meet the frequency changes between the on chip data processing units and the off chip data storage resources. The MPSoC has been implemented in FPGA to verify functionality. The experiment results show that the proposed MPSoC prototype can steadily run at 90 MHz, providing the memory throughput of 2880Mbps.