Power analysis methodology for secure circuits
Kamil Gomina, Jean-Baptiste Rigaud, Philippe Gendrier, Ph. Candelier, Assia Tria · 2013
A study on power consumption of a digital synchronous circuit in advanced CMOS technology is performed. These technologies target low power applications allowing accurate power analysis. A model of power signature is developed to identify data related consumption using current consumption and power delivery network capacitance at design phase. In addition to digital power characterization tool, device junction capacitance is extracted and used to provide an accurate power signature. Simulations are compared to experimental traces on a synchronous digital circuit to validate the approach. This model can also be used for complex analog/digital circuit. Finally two countermeasures masking and decoupling capacitance flattening are analyzed with our methodology in early design phase allowing to anticipate silicon tests.