Design and Verification of Large-Scale Computers by Using DDL
Nobuaki Kawato, Takao Saito, Fumihiro Maruyama, Takao Uehara · Design Automation Conference · 1979
This paper describes the total support system for DDL which has been approved by design engineers at Fujitsu. A simulator is used not only at register transfer level but also with gate level description. The translator generates gate level designs which are then optimized by designers. The verifier has powerful functions to detect conflicts in specification and its implementation.