Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture
Jin Guo, Antonis Papanikolaou, Pol Marchal, Francky Catthoor · 2006
The increasing gap between design productivity and chip complexity, and the emerging Systems-On-Chip (SOC) architectural template have led to the wide utilization of reusable Intellectual Property (IP) cores. The physical design implementation of the macro cells (IP blocks or pre-designed blocks) in general needs to find a well balanced solution among chip area, on-chip interconnect energy and critical path delay. We are especially interested in the entire trade-off curve among these three criteria at the floorplanning stage. We show this concept for a real communication scheme based on segmented bus, rather than just an extreme solution. A fast exploration design flow from the memory organization to the final layout is introduced to explore the design space.