An artwork design verification system
Henry S. Baird, Y. E. Cho · Design Automation Conference · 1975
Manual and semi-automatic methods of Integrated circuit layout are prone to errors which are often detected only after a sample chip has been fabricated. This paper describes two design verification programs that detect and identify such errors earlier in the design cycle through comparing a designer's logic description with the finished mask artwork. These programs are part of an integrated CAD system developed at RCA laboratories.