RTL synthesis with physical and controller information
Min Xu, Fadi Kurdahi · European Design and Test Conference · 1997
The current technology advances towards deep submicron have made it indispensable to consider layout and controller effects during all phases of chip synthesis. This paper proposes a paradigm for incorporating such information when synthesizing an RTL design from a scheduled behavioral specification. Experimental results corroborate the fact that layout and controller effects on chip area and performance are significant and can not be ignored.