Logic synthesis for ASICs
Robert F. Damiano, Douglas S. Reeves · IEEE Spectrum · 1991
The steps performed by logic synthesis software, which transforms a specification of a function and its timing into an application-specific integrated circuit (ASIC) such as a gate or standard cell array, programmable logic device (PLD), or field programmable gate array (FPGA), are outlined. Hardware description languages, foundry pacts, and testability are discussed. A table describing representative software packages is given.>