Fast dynamic binary rewriting to support thread migration in shared-ISA asymmetric multicores
Giorgis Georgakoudis, Dimitrios S. Nikolopoulos, Spyros Lalis · 2013
Asymmetric multicore processors have demonstrated a strong potential for improving performance and energy-efficiency. Shared-ISA asymmetric multicore processors overcome programmability problems in disjoint-ISA systems and enhance single-ISA architectures with instruction based asymmetry. In such a design, processors share a common, baseline ISA and performance enhanced (PE) cores extend the baseline ISA with instructions that accelerate performance-critical operations. To exploit asymmetry, the scheduler should be able to migrate threads based on their acceleration potential.