FPGA-based testing strategy for cryptographic chips: A case study on Elliptic Curve Processor for RFID tags
Junfeng Fan, Miroslav Knežević, Duško Karaklajić, Roel Maes, Vladimir Rožić, Lejla Batina, Ingrid M.R. Verbauwhede · 2009
Testing of cryptographic chips or components has one extra dimension: physical security. The chip designers should improve the design if it leaks too much information through side-channels, such as timing, power consumption, electric-magnetic radiation, and so on. This requires an evaluation of the security level of the chip under different side-channel attacks before it is manufactured. This paper presents an FPGA-based testing strategy for cryptographic chips. Using a block-based architecture, a testing bus and a shadow FPGA, we are able to check information leakage of each block. We describe this strategy with an Elliptic Curve Cryptosystem (ECC) for RFID tags.