An efficient parallel systolic array for AB2 over GF(2m)
Kee-Won Kim, Won-Jin Lee · IEICE Electronics Express · 2013
This paper presents an efficient parallel-in parallel-out systolic array for AB2 over GF(2m) using the polynomial basis. As compared to existing related systolic arrays, the proposed array gains a significant reduction in hardware complexity. The proposed architecture includes the features of regularity, modularity and local interconnection. Accordingly, it is well suited for VLSI implementation and can be easily applied as a basic architecture for computing an inversion/division operation.