An FPGA implementation of whitted-style ray tracing accelerator
Woo-Chan Park, Jae‐Ho Nah, Jeong‐Soo Park, Kyungho Lee, Dongseok Kim, Sang-Duk Kim, Jin‐Hong Park, Cheong-Ghil Kim, Yoon-Sig Kang, Sung-Bong Yang, Tack‐Don Han · 2008
This paper presents an FPGA implementation of a full whitted-style ray tracing accelerator. It achieves about 1.3 M rays per second over realistic 3 D scenes. The future implementation with ASIC is expected to achieve real-time performance.