Analog system verification in the presence of parasitics using behavioral simulation
Edward W. Y. Liu, Henry C. Chang, Alberto Luigi Sangiovanni-Vincentelli · 1993
In analog system design, final verification in the presence of parasitic loading effects is crucial to guarantee functionality of the entire circuit.In this paper, we present a methodology for analog system verification in the presence of parasitic using behavioral simulation.When applied to a synthesized 10 bit D/A, our approach is accurate to 0.005 LSB compared with SPICE, while being several orders of magnitude faster.