End-to-End Adaptive Packet Aggregation for High-Throughput I/O Bus Network Using Ethernet
Jun Suzuki, Yuki Hayashi, Masaki Kan, Shinya Miyakawa, Takashi Yoshikawa · 2014
Input/output (I/O) bus networks using Ethernets transfer a PCI Express (PCIe) I/O packet between a host and an I/O device by encapsulating it into an Ethernet frame. Because the size of PCIe packets is generally small in such systems, the overhead to individually encapsulate them into Ethernet frames lowers the PCIe throughput provided by Ethernet connections. This decrease in throughput directly degrades the performance of I/O devices, which transmit high-throughput PCIe traffic. Examples of such devices include PCIe solid-state drives and graphics processing units. We propose a method of aggregating multiple PCIe packets into a single Ethernet frame in an end-to-end manner to provide a high-throughput PCIe connection. The aggregation is performed at the bottleneck-link rate of the Ethernet path through which those packets are transferred. The number of aggregated PCIe packets is adaptively determined by aggregating ones that reside in a transmission queue when it is scheduled to transmit packets. This enables low-latency throughput enhancement because the proposed method does not increase the transmission latency of PCIe packets by waiting for more packets to aggregate. In addition, it does not require individual configuration of operation parameters, such as aggregation threshold and time out value, depending on the rate of the PCIe traffic of I/O devices. We implemented our method in a PCIe-to-Ethernet bridge prototype using a field-programmable gate array. As a result, I/O performance improved up to 41%.