Computing RAMs for media processing
Duncan G. Elliott, W. Martin Snelgrove, Christian Cojocaru, Michael Stumm · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 1997
Integrating processing elements in DRAM makes very large bus widths available: at least 2K processing elements fit in a 4 Mb chip or 4 K in a 16 Mb DRAM. The processors can add an area overhead as low as 10% and power overhead of about 10 - 25%. To get these efficiencies, the processors have to be pitch-matched to the DRAM. Interprocessor communication is also severely limited, especially when going 'off-chip' while retaining low-cost packaging. These 'computing RAMs' (C$CCLRAM) can form the main memory for SISD or MIMD hosts, making their contributions to the computing load scalable. The SIMD nature of C$CCLRAM matches large image-processing tasks with high uniformity and locality of reference, making real-time DCT, anti-aliasing and a variety of transformations available at the low cost required for consumer applications. Even given a PE 'budget' of 70 - 200 transistors, and with the limited interconnect characteristic of low-cost DRAM, there are quite a few architectural choices available to the computer architect. These can be made to favor the data widths and operations needed for image processing while retaining good generality.