Fault injection emulator for field programmable gate arrays
Thomas Slaughter, Charles E. Stroud, John M. Emmert, B. Skaggs · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2001
As the prevalence and size of Field Programmable Gate Arrays (FPGAs) has increased, so too has the complexity of manufacturing testing and defect diagnosis for yield enhancement. The re-programmability of FPGAs has attracted considerable interest in the ability to re-program a system function to avoid any known faults. As a result, various test, diagnostic, and fault tolerant techniques have been developed for FPGAs. However, the evaluation of the effectiveness of these techniques is nearly impossible using traditional fault simulation techniques due to the size and complexity of current FPGAs. We have developed an emulation procedure to inject faults into FPGAs in such a way that the faults are actually emulated in the physical FPGA. By determining proper bit locations within the configuration memory of the FPGA, download files used to program the FPGA can be manipulated to emulate faults including stuck-at faults, bridging faults, and opens in the programmable logic and routing resources of the FPGA. Almost any combination faults can be emulated spatially (allowing for either clustering or random distributions) and/or temporally (allowing for the simulation of burst or random faults over time).