An interleaved array-processing architecture
J. Robert Jump, James D. Wise, D.T. Harper · AFIPS conference proceedings · 1984
This paper describes an array-processing architecture capable of executing high-level vector operations. There are two distinguishing features of this architecture: First, the user can define for later use complex vector operations that involve several arithmetic operations and branching. Once defined, they appear as built-in vector instructions to the user. Second, the algorithms for accessing and aligning vectors are implemented in hardware, eliminating the need for user programs to deal with memory addresses.