Optimum design of multistage synchronous sampling rate converter
Takahiro Asai · Electronics and Communications in Japan (Part III Fundamental Electronic Science) · 2002
Abstract This paper studies the optimum design of a multistage synchronous rate converter consisting of cascaded interpolation circuits by the window method. Two design approaches are proposed. One is a “simple design method” with a good perspective but a limited applicable range. The other is a “general‐purpose design method” that can be applied widely. In this paper, the former is mainly used. The signals are assumed to have a flat spectrum. As the cumulative product rule of the conversion error, the power sum is assumed. By providing the signal bandwidth, required conversion error, and total interpolation rate, optimum values are derived for the half width of the window in each stage and the interpolation rate that minimizes the number of multiplications and the interpolation coefficients. In the range where the “simple design method” is valid (where the signal bandwidth is relatively narrow), the optimum conditions for the number of calculations and for the total number of interpolation coefficients are the same. Then, the dependence of the number of calculations and the total number of interpolation coefficients as well as of the total interpolation rate and the total number of interpolation coefficients is found. A design example is presented. It is shown that highly accurate rate conversion is possible with few calculations. Further, according to the “general‐purpose design method,” it is possible to treat signals with a broad bandwidth (such as 0.92ϕ). © 2002 Wiley Periodicals, Inc. Electron Comm Jpn Pt 3, 86(4): 26–37, 2003; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/ecjc.10015